0x50000000: Analog-to-Digital Converter
170/170 fields covered. Toggle Registers.
configuration register
Offset: 0xC, reset: 0x00000000, access: read-write
18/18 fields covered.
Bits 6-9: EXTSEL.
Allowed values:
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
sample time register 1
Offset: 0x14, reset: 0x00000000, access: read-write
9/9 fields covered.
Bits 3-5: SMP1.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 6-8: SMP2.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 9-11: SMP3.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 12-14: SMP4.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 15-17: SMP5.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 18-20: SMP6.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 21-23: SMP7.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 24-26: SMP8.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 27-29: SMP9.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
sample time register 2
Offset: 0x18, reset: 0x00000000, access: read-write
9/9 fields covered.
Bits 0-2: SMP10.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 3-5: SMP11.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 6-8: SMP12.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 9-11: SMP13.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 12-14: SMP14.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 15-17: SMP15.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 18-20: SMP16.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 21-23: SMP17.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 24-26: SMP18.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
watchdog threshold register 1
Offset: 0x20, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT1
rw |
|||||||||||||||
watchdog threshold register
Offset: 0x24, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT2
rw |
|||||||||||||||
watchdog threshold register 3
Offset: 0x28, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT3
rw |
|||||||||||||||
regular sequence register 4
Offset: 0x3C, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SQ16
rw |
SQ15
rw |
||||||||||||||
regular Data Register
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDATA
r |
|||||||||||||||
offset register 1
Offset: 0x60, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET1_EN
rw |
OFFSET1_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET1
rw |
|||||||||||||||
offset register 2
Offset: 0x64, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET2_EN
rw |
OFFSET2_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET2
rw |
|||||||||||||||
offset register 3
Offset: 0x68, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET3_EN
rw |
OFFSET3_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET3
rw |
|||||||||||||||
offset register 4
Offset: 0x6C, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET4_EN
rw |
OFFSET4_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET4
rw |
|||||||||||||||
injected data register 1
Offset: 0x80, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA1
r |
|||||||||||||||
injected data register 2
Offset: 0x84, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA2
r |
|||||||||||||||
injected data register 3
Offset: 0x88, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA3
r |
|||||||||||||||
injected data register 4
Offset: 0x8C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA4
r |
|||||||||||||||
Analog Watchdog 2 Configuration Register
Offset: 0xA0, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD2CH17
rw |
AWD2CH16
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD2CH15
rw |
AWD2CH14
rw |
AWD2CH13
rw |
AWD2CH12
rw |
AWD2CH11
rw |
AWD2CH10
rw |
AWD2CH9
rw |
AWD2CH8
rw |
AWD2CH7
rw |
AWD2CH6
rw |
AWD2CH5
rw |
AWD2CH4
rw |
AWD2CH3
rw |
AWD2CH2
rw |
AWD2CH1
rw |
AWD2CH0
rw |
Analog Watchdog 3 Configuration Register
Offset: 0xA4, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD3CH17
rw |
AWD3CH16
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD3CH15
rw |
AWD3CH14
rw |
AWD3CH13
rw |
AWD3CH12
rw |
AWD3CH11
rw |
AWD3CH10
rw |
AWD3CH9
rw |
AWD3CH8
rw |
AWD3CH7
rw |
AWD3CH6
rw |
AWD3CH5
rw |
AWD3CH4
rw |
AWD3CH3
rw |
AWD3CH2
rw |
AWD3CH1
rw |
AWD3CH0
rw |
Differential Mode Selection Register 2
Offset: 0xB0, reset: 0x00000000, access: Unspecified
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIFSEL_117
N/A |
DIFSEL_116
N/A |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIFSEL_115
N/A |
DIFSEL_114
N/A |
DIFSEL_113
N/A |
DIFSEL_112
N/A |
DIFSEL_111
N/A |
DIFSEL_110
N/A |
DIFSEL_19
N/A |
DIFSEL_18
N/A |
DIFSEL_17
N/A |
DIFSEL_16
N/A |
DIFSEL_15
N/A |
DIFSEL_14
N/A |
DIFSEL_13
N/A |
DIFSEL_12
N/A |
DIFSEL_11
N/A |
DIFSEL_10
N/A |
Calibration Factors
Offset: 0xB4, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CALFACT_D
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALFACT_S
rw |
|||||||||||||||
0x50000100: Analog-to-Digital Converter
170/170 fields covered. Toggle Registers.
configuration register
Offset: 0xC, reset: 0x00000000, access: read-write
18/18 fields covered.
Bits 6-9: EXTSEL.
Allowed values:
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
sample time register 1
Offset: 0x14, reset: 0x00000000, access: read-write
9/9 fields covered.
Bits 3-5: SMP1.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 6-8: SMP2.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 9-11: SMP3.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 12-14: SMP4.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 15-17: SMP5.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 18-20: SMP6.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 21-23: SMP7.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 24-26: SMP8.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 27-29: SMP9.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
sample time register 2
Offset: 0x18, reset: 0x00000000, access: read-write
9/9 fields covered.
Bits 0-2: SMP10.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 3-5: SMP11.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 6-8: SMP12.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 9-11: SMP13.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 12-14: SMP14.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 15-17: SMP15.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 18-20: SMP16.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 21-23: SMP17.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
Bits 24-26: SMP18.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles
watchdog threshold register 1
Offset: 0x20, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT1
rw |
|||||||||||||||
watchdog threshold register
Offset: 0x24, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT2
rw |
|||||||||||||||
watchdog threshold register 3
Offset: 0x28, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT3
rw |
|||||||||||||||
regular sequence register 4
Offset: 0x3C, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SQ16
rw |
SQ15
rw |
||||||||||||||
regular Data Register
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDATA
r |
|||||||||||||||
offset register 1
Offset: 0x60, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET1_EN
rw |
OFFSET1_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET1
rw |
|||||||||||||||
offset register 2
Offset: 0x64, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET2_EN
rw |
OFFSET2_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET2
rw |
|||||||||||||||
offset register 3
Offset: 0x68, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET3_EN
rw |
OFFSET3_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET3
rw |
|||||||||||||||
offset register 4
Offset: 0x6C, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFFSET4_EN
rw |
OFFSET4_CH
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OFFSET4
rw |
|||||||||||||||
injected data register 1
Offset: 0x80, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA1
r |
|||||||||||||||
injected data register 2
Offset: 0x84, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA2
r |
|||||||||||||||
injected data register 3
Offset: 0x88, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA3
r |
|||||||||||||||
injected data register 4
Offset: 0x8C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA4
r |
|||||||||||||||
Analog Watchdog 2 Configuration Register
Offset: 0xA0, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD2CH17
rw |
AWD2CH16
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD2CH15
rw |
AWD2CH14
rw |
AWD2CH13
rw |
AWD2CH12
rw |
AWD2CH11
rw |
AWD2CH10
rw |
AWD2CH9
rw |
AWD2CH8
rw |
AWD2CH7
rw |
AWD2CH6
rw |
AWD2CH5
rw |
AWD2CH4
rw |
AWD2CH3
rw |
AWD2CH2
rw |
AWD2CH1
rw |
AWD2CH0
rw |
Analog Watchdog 3 Configuration Register
Offset: 0xA4, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD3CH17
rw |
AWD3CH16
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD3CH15
rw |
AWD3CH14
rw |
AWD3CH13
rw |
AWD3CH12
rw |
AWD3CH11
rw |
AWD3CH10
rw |
AWD3CH9
rw |
AWD3CH8
rw |
AWD3CH7
rw |
AWD3CH6
rw |
AWD3CH5
rw |
AWD3CH4
rw |
AWD3CH3
rw |
AWD3CH2
rw |
AWD3CH1
rw |
AWD3CH0
rw |
Differential Mode Selection Register 2
Offset: 0xB0, reset: 0x00000000, access: Unspecified
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIFSEL_117
N/A |
DIFSEL_116
N/A |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIFSEL_115
N/A |
DIFSEL_114
N/A |
DIFSEL_113
N/A |
DIFSEL_112
N/A |
DIFSEL_111
N/A |
DIFSEL_110
N/A |
DIFSEL_19
N/A |
DIFSEL_18
N/A |
DIFSEL_17
N/A |
DIFSEL_16
N/A |
DIFSEL_15
N/A |
DIFSEL_14
N/A |
DIFSEL_13
N/A |
DIFSEL_12
N/A |
DIFSEL_11
N/A |
DIFSEL_10
N/A |
Calibration Factors
Offset: 0xB4, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CALFACT_D
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALFACT_S
rw |
|||||||||||||||
0x50000300: ADC common registers
32/32 fields covered. Toggle Registers.
ADC Common status register
Offset: 0x0, reset: 0x00000000, access: read-only
22/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JQOVF_SLV
r |
AWD3_SLV
r |
AWD2_SLV
r |
AWD1_SLV
r |
JEOS_SLV
r |
JEOC_SLV
r |
OVR_SLV
r |
EOS_SLV
r |
EOC_SLV
r |
EOSMP_SLV
r |
ADRDY_SLV
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JQOVF_MST
r |
AWD3_MST
r |
AWD2_MST
r |
AWD1_MST
r |
JEOS_MST
r |
JEOC_MST
r |
OVR_MST
r |
EOS_MST
r |
EOC_MST
r |
EOSMP_MST
r |
ADRDY_MST
r |
|||||
ADC common control register
Offset: 0x8, reset: 0x00000000, access: read-write
8/8 fields covered.
Bits 0-4: Dual ADC mode selection.
Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only
Bits 16-17: ADC clock mode.
Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4
ADC common regular data register for dual mode
Offset: 0xC, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDATA_SLV
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDATA_MST
r |
|||||||||||||||
0x40006400: Controller area network
57/280 fields covered. Toggle Registers.
receive FIFO 0 register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFOM
rw |
FOVR
rw |
FULL
rw |
FMP
r |
||||||||||||
filter master register
Offset: 0x200, reset: 0x2A1C0E01, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CAN2SB
rw |
FINIT
rw |
||||||||||||||
filter mode register
Offset: 0x204, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FBM27
rw |
FBM26
rw |
FBM25
rw |
FBM24
rw |
FBM23
rw |
FBM22
rw |
FBM21
rw |
FBM20
rw |
FBM19
rw |
FBM18
rw |
FBM17
rw |
FBM16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FBM15
rw |
FBM14
rw |
FBM13
rw |
FBM12
rw |
FBM11
rw |
FBM10
rw |
FBM9
rw |
FBM8
rw |
FBM7
rw |
FBM6
rw |
FBM5
rw |
FBM4
rw |
FBM3
rw |
FBM2
rw |
FBM1
rw |
FBM0
rw |
filter scale register
Offset: 0x20C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FSC27
rw |
FSC26
rw |
FSC25
rw |
FSC24
rw |
FSC23
rw |
FSC22
rw |
FSC21
rw |
FSC20
rw |
FSC19
rw |
FSC18
rw |
FSC17
rw |
FSC16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSC15
rw |
FSC14
rw |
FSC13
rw |
FSC12
rw |
FSC11
rw |
FSC10
rw |
FSC9
rw |
FSC8
rw |
FSC7
rw |
FSC6
rw |
FSC5
rw |
FSC4
rw |
FSC3
rw |
FSC2
rw |
FSC1
rw |
FSC0
rw |
filter FIFO assignment register
Offset: 0x214, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FFA27
rw |
FFA26
rw |
FFA25
rw |
FFA24
rw |
FFA23
rw |
FFA22
rw |
FFA21
rw |
FFA20
rw |
FFA19
rw |
FFA18
rw |
FFA17
rw |
FFA16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FFA15
rw |
FFA14
rw |
FFA13
rw |
FFA12
rw |
FFA11
rw |
FFA10
rw |
FFA9
rw |
FFA8
rw |
FFA7
rw |
FFA6
rw |
FFA5
rw |
FFA4
rw |
FFA3
rw |
FFA2
rw |
FFA1
rw |
FFA0
rw |
CAN filter activation register
Offset: 0x21C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FACT27
rw |
FACT26
rw |
FACT25
rw |
FACT24
rw |
FACT23
rw |
FACT22
rw |
FACT21
rw |
FACT20
rw |
FACT19
rw |
FACT18
rw |
FACT17
rw |
FACT16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FACT15
rw |
FACT14
rw |
FACT13
rw |
FACT12
rw |
FACT11
rw |
FACT10
rw |
FACT9
rw |
FACT8
rw |
FACT7
rw |
FACT6
rw |
FACT5
rw |
FACT4
rw |
FACT3
rw |
FACT2
rw |
FACT1
rw |
FACT0
rw |
1073807360: General purpose comparators
21/24 fields covered. Toggle Registers.
control and status register
Offset: 0x32, reset: 0, access: Unspecified
7/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COMP2LOCK
rw |
COMP2OUT
r |
COMP2INMSEL3
rw |
COMP2_BLANKING
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
COMP2POL
rw |
COMP2OUTSEL
rw |
COMP2INMSEL
rw |
COMP2EN
rw |
||||||||||||
Bits 10-13: Comparator 2 output selection.
Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer1OCRefClearInput: Timer 1 OCREF_CLR input
7: Timer1InputCapture1: Timer 1 input capture 1
8: Timer2InputCapture4: Timer 2 input capture 4
9: Timer2OCRefClearInput: Timer 2 OCREF_CLR input
10: Timer3InputCapture1: Timer 3 input capture 1
11: Timer3OCRefClearInput: Timer 3 OCREF_CLR input
control and status register
Offset: 0x40, reset: 0, access: Unspecified
7/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COMP4LOCK
rw |
COMP4OUT
r |
COMP4INMSEL3
rw |
COMP4_BLANKING
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
COMP4POL
rw |
COMP4OUTSEL
rw |
COMP4INMSEL
rw |
COMP4EN
rw |
||||||||||||
Bits 10-13: Comparator 4 output selection.
Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer3InputCapture3: Timer 3 input capture 3
8: Timer15InputCapture2: Timer 15 input capture 2
10: Timer15OCRefClearInput: Timer 15 OCREF_CLR input
11: Timer3OCRefClearInput: Timer 3 OCREF_CLR input
control and status register
Offset: 0x48, reset: 0, access: Unspecified
7/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COMP6LOCK
rw |
COMP6OUT
r |
COMP6INMSEL3
rw |
COMP6_BLANKING
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
COMP6POL
rw |
COMP6OUTSEL
rw |
COMP6INMSEL
rw |
COMP6EN
rw |
||||||||||||
Bits 10-13: Comparator 6 output selection.
Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer2InputCapture2: Timer 2 input capture 2
8: Timer2OCRefClearInput: Timer 2 OCREF_CLR input
9: Timer16OCRefClearInput: Timer 16 OCREF_CLR input
10: Timer16InputCapture1: Timer 16 input capture 1
0x40023000: cyclic redundancy check calculation unit
10/10 fields covered. Toggle Registers.
Data register - half-word sized
Offset: 0x0, reset: 65535, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR16
rw |
|||||||||||||||
Independent data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IDR
rw |
|||||||||||||||
Control register
Offset: 0x8, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REV_OUT
rw |
REV_IN
rw |
POLYSIZE
rw |
RESET
rw |
||||||||||||
Initial CRC value
Offset: 0x10, reset: 0xFFFFFFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INIT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INIT
rw |
|||||||||||||||
CRC polynomial
Offset: 0x14, reset: 0x04C11DB7, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
POL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
POL
rw |
|||||||||||||||
0x40007400: Digital-to-analog converter
34/34 fields covered. Toggle Registers.
control register
Offset: 0x0, reset: 0x00000000, access: read-write
16/16 fields covered.
Bits 19-21: DAC channel2 trigger selection.
Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger
software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWTRIG2
w |
SWTRIG1
w |
||||||||||||||
channel1 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 12-bit left aligned data holding register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel2 12-bit right aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 8-bit right-aligned data holding register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
DACC1DHR
rw |
||||||||||||||
channel1 data output register
Offset: 0x2C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DOR
r |
|||||||||||||||
channel2 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DOR
r |
|||||||||||||||
status register
Offset: 0x34, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAUDR1
rw |
|||||||||||||||
0x40009800: Digital-to-analog converter
34/34 fields covered. Toggle Registers.
control register
Offset: 0x0, reset: 0x00000000, access: read-write
16/16 fields covered.
Bits 19-21: DAC channel2 trigger selection.
Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger
software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWTRIG2
w |
SWTRIG1
w |
||||||||||||||
channel1 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 12-bit left aligned data holding register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel2 12-bit right aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 8-bit right-aligned data holding register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
DACC1DHR
rw |
||||||||||||||
channel1 data output register
Offset: 0x2C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DOR
r |
|||||||||||||||
channel2 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DOR
r |
|||||||||||||||
status register
Offset: 0x34, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAUDR1
rw |
|||||||||||||||
0xE0042000: Debug support
2/27 fields covered. Toggle Registers.
MCU Device ID Code Register
Offset: 0x0, reset: 0x0, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REV_ID
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEV_ID
r |
|||||||||||||||
Debug MCU Configuration Register
Offset: 0x4, reset: 0x0, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRACE_MODE
rw |
TRACE_IOEN
rw |
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG_SLEEP
rw |
|||||||||||
APB Low Freeze Register
Offset: 0x8, reset: 0x0, access: read-write
0/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_CAN_STOP
rw |
I2C2_SMBUS_TIMEOUT
rw |
I2C1_SMBUS_TIMEOUT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_STOP
rw |
DBG_TIM18_STOP
rw |
DBG_TIMER14_STOP
rw |
DBG_TIM13_STOP
rw |
DBG_TIM12_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM5_STOP
rw |
DBG_TIM4_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIM2_STOP
rw |
|||
APB High Freeze Register
Offset: 0xC, reset: 0x0, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_TIM19_STOP
rw |
DBG_TIM17_STO
rw |
DBG_TIM16_STOP
rw |
DBG_TIM15_STOP
rw |
||||||||||||
0x40020000: DMA controller 1
69/71 fields covered. Toggle Registers.
DMA interrupt status register (DMA_ISR)
Offset: 0x0, reset: 0x00000000, access: read-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEIF7
r |
HTIF7
r |
TCIF7
r |
GIF7
r |
TEIF6
r |
HTIF6
r |
TCIF6
r |
GIF6
r |
TEIF5
r |
HTIF5
r |
TCIF5
r |
GIF5
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TEIF4
r |
HTIF4
r |
TCIF4
r |
GIF4
r |
TEIF3
r |
HTIF3
r |
TCIF3
r |
GIF3
r |
TEIF2
r |
HTIF2
r |
TCIF2
r |
GIF2
r |
TEIF1
r |
HTIF1
r |
TCIF1
r |
GIF1
r |
DMA interrupt flag clear register (DMA_IFCR)
Offset: 0x4, reset: 0x00000000, access: write-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTEIF7
w |
CHTIF7
w |
CTCIF7
w |
CGIF7
w |
CTEIF6
w |
CHTIF6
w |
CTCIF6
w |
CGIF6
w |
CTEIF5
w |
CHTIF5
w |
CTCIF5
w |
CGIF5
w |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CTEIF4
w |
CHTIF4
w |
CTCIF4
w |
CGIF4
w |
CTEIF3
w |
CHTIF3
w |
CTCIF3
w |
CGIF3
w |
CTEIF2
w |
CHTIF2
w |
CTCIF2
w |
CGIF2
w |
CTEIF1
w |
CHTIF1
w |
CTCIF1
w |
CGIF1
w |
DMA channel 1 peripheral address register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address register
Offset: 0xC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
0x40010400: External interrupt/event controller
184/184 fields covered. Toggle Registers.
Interrupt mask register
Offset: 0x0, reset: 0x1F800000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MR31
rw |
MR30
rw |
MR29
rw |
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Event mask register
Offset: 0x4, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MR31
rw |
MR30
rw |
MR29
rw |
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Software interrupt event register
Offset: 0x10, reset: 0x00000000, access: read-write
26/26 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SWIER31
rw |
SWIER30
rw |
SWIER29
rw |
SWIER22
rw |
SWIER21
rw |
SWIER20
rw |
SWIER19
rw |
SWIER18
rw |
SWIER17
rw |
SWIER16
rw |
||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWIER15
rw |
SWIER14
rw |
SWIER13
rw |
SWIER12
rw |
SWIER11
rw |
SWIER10
rw |
SWIER9
rw |
SWIER8
rw |
SWIER7
rw |
SWIER6
rw |
SWIER5
rw |
SWIER4
rw |
SWIER3
rw |
SWIER2
rw |
SWIER1
rw |
SWIER0
rw |
Interrupt mask register
Offset: 0x18, reset: 0xFFFFFFFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR35
rw |
MR34
rw |
MR33
rw |
MR32
rw |
||||||||||||
Event mask register
Offset: 0x1C, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR35
rw |
MR34
rw |
MR33
rw |
MR32
rw |
||||||||||||
Rising Trigger selection register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TR33
rw |
TR32
rw |
||||||||||||||
Falling Trigger selection register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TR33
rw |
TR32
rw |
||||||||||||||
Software interrupt event register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWIER33
rw |
SWIER32
rw |
||||||||||||||
Pending register
Offset: 0x2C, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR33
rw |
PR32
rw |
||||||||||||||
0x40022000: Flash
33/33 fields covered. Toggle Registers.
Flash access control register
Offset: 0x0, reset: 0x00000030, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRFTBS
r |
PRFTBE
rw |
HLFCYA
rw |
LATENCY
rw |
||||||||||||
Flash key register
Offset: 0x4, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FKEYR
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FKEYR
w |
|||||||||||||||
Flash option key register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OPTKEYR
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OPTKEYR
w |
|||||||||||||||
Flash status register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOP
rw |
WRPRTERR
rw |
PGERR
rw |
BSY
r |
||||||||||||
Flash address register
Offset: 0x14, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FAR
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FAR
w |
|||||||||||||||
Option byte register
Offset: 0x1C, reset: 0xFFFFFF02, access: read-only
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Data1
r |
Data0
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SRAM_PARITY_CHECK
r |
VDDA_MONITOR
r |
nBOOT1
r |
nRST_STDBY
r |
nRST_STOP
r |
WDG_SW
r |
RDPRT
r |
OPTERR
r |
||||||||
Write protection register
Offset: 0x20, reset: 0xFFFFFFFF, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WRP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WRP
r |
|||||||||||||||
0xE000EF34: Floting point unit
0/24 fields covered. Toggle Registers.
Floating-point context address register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDRESS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDRESS
rw |
|||||||||||||||
0xE000ED88: Floating point unit CPACR
0/1 fields covered. Toggle Registers.
Coprocessor access control register
Offset: 0x0, reset: 0x0000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x48000000: General-purpose I/Os
177/177 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x48000400: General-purpose I/Os
177/177 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x48000800: General-purpose I/Os
177/177 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x48000C00: General-purpose I/Os
177/177 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x48001400: General-purpose I/Os
177/177 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40017780: High Resolution Timer: Common functions
436/436 fields covered. Toggle Registers.
Control Register 1
Offset: 0x0, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 16-18: ADC Trigger 1 Update Source.
Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E
Bits 19-21: ADC Trigger 2 Update Source.
Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E
Bits 22-24: ADC Trigger 3 Update Source.
Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E
Bits 25-27: ADC Trigger 4 Update Source.
Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E
Burst Mode Control Register
Offset: 0x20, reset: 0x00000000, access: read-write
12/12 fields covered.
Bits 2-5: Burst Mode Clock source.
Allowed values:
0: Master: Master timer reset/roll-over
1: TimerA: Timer A counter reset/roll-over
2: TimerB: Timer B counter reset/roll-over
3: TimerC: Timer C counter reset/roll-over
4: TimerD: Timer D counter reset/roll-over
5: TimerE: Timer E counter reset/roll-over
6: Event1: On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock
7: Event2: On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock
8: Event3: On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock
9: Event4: On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock
10: Clock: Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting
Bits 6-9: Burst Mode Prescaler.
Allowed values:
0: Div1: Clock not divided
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16
5: Div32: Division by 32
6: Div64: Division by 64
7: Div128: Division by 128
8: Div256: Division by 256
9: Div512: Division by 512
10: Div1024: Division by 1024
11: Div2048: Division by 2048
12: Div4096: Division by 4096
13: Div8192: Division by 8192
14: Div16384: Division by 16384
15: Div32768: Division by 32768
BMTRGR
Offset: 0x24, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OCHPEV
rw |
EEV8
rw |
EEV7
rw |
TDEEV8
rw |
TAEEV7
rw |
TECMP2
rw |
TECMP1
rw |
TEREP
rw |
TERST
rw |
TDCMP2
rw |
TDCMP1
rw |
TDREP
rw |
TDRST
rw |
TCCMP2
rw |
TCCMP1
rw |
TCREP
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TCRST
rw |
TBCMP2
rw |
TBCMP1
rw |
TBREP
rw |
TBRST
rw |
TACMP2
rw |
TACMP1
rw |
TAREP
rw |
TARST
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTREP
rw |
MSTRST
rw |
SW
rw |
BMCMPR
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BMCMP
rw |
|||||||||||||||
Burst Mode Period Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BMPER
rw |
|||||||||||||||
Timer External Event Control Register 1
Offset: 0x30, reset: 0x00000000, access: read-write
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EE5FAST
rw |
EE5SNS
rw |
EE5POL
rw |
EE5SRC
rw |
EE4FAST
rw |
EE4SNS
rw |
EE4POL
rw |
EE4SRC
rw |
EE3FAST
rw |
EE3SNS
rw |
||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EE3SNS
rw |
EE3POL
rw |
EE3SRC
rw |
EE2FAST
rw |
EE2SNS
rw |
EE2POL
rw |
EE2SRC
rw |
EE1FAST
rw |
EE1SNS
rw |
EE1POL
rw |
EE1SRC
rw |
|||||
Timer External Event Control Register 3
Offset: 0x38, reset: 0x00000000, access: read-write
6/6 fields covered.
Bits 0-3: EE6F.
Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 6-9: EE7F.
Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 12-15: EE8F.
Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 18-21: EE9F.
Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 24-27: EE10F.
Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
ADC Trigger 1 Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AD1TEPER
rw |
AD1TEC4
rw |
AD1TEC3
rw |
AD1TEC2
rw |
AD1TDPER
rw |
AD1TDC4
rw |
AD1TDC3
rw |
AD1TDC2
rw |
AD1TCPER
rw |
AD1TCC4
rw |
AD1TCC3
rw |
AD1TCC2
rw |
AD1TBRST
rw |
AD1TBPER
rw |
AD1TBC4
rw |
AD1TBC3
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AD1TBC2
rw |
AD1TARST
rw |
AD1TAPER
rw |
AD1TAC4
rw |
AD1TAC3
rw |
AD1TAC2
rw |
AD1EEV5
rw |
AD1EEV4
rw |
AD1EEV3
rw |
AD1EEV2
rw |
AD1EEV1
rw |
AD1MPER
rw |
AD1MC4
rw |
AD1MC3
rw |
AD1MC2
rw |
AD1MC1
rw |
ADC Trigger 2 Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AD2TERST
rw |
AD2TEC4
rw |
AD2TEC3
rw |
AD2TEC2
rw |
AD2TDRST
rw |
AD2TDPER
rw |
AD2TDC4
rw |
AD2TDC3
rw |
AD2TDC2
rw |
AD2TCRST
rw |
AD2TCPER
rw |
AD2TCC4
rw |
AD2TCC3
rw |
AD2TCC2
rw |
AD2TBPER
rw |
AD2TBC4
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AD2TBC3
rw |
AD2TBC2
rw |
AD2TAPER
rw |
AD2TAC4
rw |
AD2TAC3
rw |
AD2TAC2
rw |
AD2EEV10
rw |
AD2EEV9
rw |
AD2EEV8
rw |
AD2EEV7
rw |
AD2EEV6
rw |
AD2MPER
rw |
AD2MC4
rw |
AD2MC3
rw |
AD2MC2
rw |
AD2MC1
rw |
ADC Trigger 3 Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AD1TEPER
rw |
AD1TEC4
rw |
AD1TEC3
rw |
AD1TEC2
rw |
AD1TDPER
rw |
AD1TDC4
rw |
AD1TDC3
rw |
AD1TDC2
rw |
AD1TCPER
rw |
AD1TCC4
rw |
AD1TCC3
rw |
AD1TCC2
rw |
AD1TBRST
rw |
AD1TBPER
rw |
AD1TBC4
rw |
AD1TBC3
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AD1TBC2
rw |
AD1TARST
rw |
AD1TAPER
rw |
AD1TAC4
rw |
AD1TAC3
rw |
AD1TAC2
rw |
AD1EEV5
rw |
AD1EEV4
rw |
AD1EEV3
rw |
AD1EEV2
rw |
AD1EEV1
rw |
AD1MPER
rw |
AD1MC4
rw |
AD1MC3
rw |
AD1MC2
rw |
AD1MC1
rw |
ADC Trigger 4 Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AD2TERST
rw |
AD2TEC4
rw |
AD2TEC3
rw |
AD2TEC2
rw |
AD2TDRST
rw |
AD2TDPER
rw |
AD2TDC4
rw |
AD2TDC3
rw |
AD2TDC2
rw |
AD2TCRST
rw |
AD2TCPER
rw |
AD2TCC4
rw |
AD2TCC3
rw |
AD2TCC2
rw |
AD2TBPER
rw |
AD2TBC4
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AD2TBC3
rw |
AD2TBC2
rw |
AD2TAPER
rw |
AD2TAC4
rw |
AD2TAC3
rw |
AD2TAC2
rw |
AD2EEV10
rw |
AD2EEV9
rw |
AD2EEV8
rw |
AD2EEV7
rw |
AD2EEV6
rw |
AD2MPER
rw |
AD2MC4
rw |
AD2MC3
rw |
AD2MC2
rw |
AD2MC1
rw |
DLL Control Register
Offset: 0x4C, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALRTE
rw |
CALEN
rw |
CAL
rw |
|||||||||||||
HRTIM Fault Input Register 1
Offset: 0x50, reset: 0x00000000, access: read-write
20/20 fields covered.
Bits 3-6: FLT1F.
Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 11-14: FLT2F.
Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 19-22: FLT3F.
Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Bits 27-30: FLT4F.
Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
HRTIM Fault Input Register 2
Offset: 0x54, reset: 0x00000000, access: read-write
6/6 fields covered.
Bits 3-6: FLT5F.
Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8
Burst DMA Timerx update Register
Offset: 0x5C, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMxFLTR
rw |
TIMxOUTR
rw |
TIMxCHPR
rw |
TIMxRSTR
rw |
TIMxEEFR2
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMxEEFR1
rw |
TIMxRST2R
rw |
TIMxSET2R
rw |
TIMxRST1R
rw |
TIMxSET1R
rw |
TIMx_DTxR
rw |
TIMxCMP4
rw |
TIMxCMP3
rw |
TIMxCMP2
rw |
TIMxCMP1
rw |
TIMxREP
rw |
TIMxPER
rw |
TIMxCNT
rw |
TIMxDIER
rw |
TIMxICR
rw |
TIMxCR
rw |
Burst DMA Timerx update Register
Offset: 0x60, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMxFLTR
rw |
TIMxOUTR
rw |
TIMxCHPR
rw |
TIMxRSTR
rw |
TIMxEEFR2
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMxEEFR1
rw |
TIMxRST2R
rw |
TIMxSET2R
rw |
TIMxRST1R
rw |
TIMxSET1R
rw |
TIMx_DTxR
rw |
TIMxCMP4
rw |
TIMxCMP3
rw |
TIMxCMP2
rw |
TIMxCMP1
rw |
TIMxREP
rw |
TIMxPER
rw |
TIMxCNT
rw |
TIMxDIER
rw |
TIMxICR
rw |
TIMxCR
rw |
Burst DMA Timerx update Register
Offset: 0x64, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMxFLTR
rw |
TIMxOUTR
rw |
TIMxCHPR
rw |
TIMxRSTR
rw |
TIMxEEFR2
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMxEEFR1
rw |
TIMxRST2R
rw |
TIMxSET2R
rw |
TIMxRST1R
rw |
TIMxSET1R
rw |
TIMx_DTxR
rw |
TIMxCMP4
rw |
TIMxCMP3
rw |
TIMxCMP2
rw |
TIMxCMP1
rw |
TIMxREP
rw |
TIMxPER
rw |
TIMxCNT
rw |
TIMxDIER
rw |
TIMxICR
rw |
TIMxCR
rw |
Burst DMA Timerx update Register
Offset: 0x68, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMxFLTR
rw |
TIMxOUTR
rw |
TIMxCHPR
rw |
TIMxRSTR
rw |
TIMxEEFR2
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMxEEFR1
rw |
TIMxRST2R
rw |
TIMxSET2R
rw |
TIMxRST1R
rw |
TIMxSET1R
rw |
TIMx_DTxR
rw |
TIMxCMP4
rw |
TIMxCMP3
rw |
TIMxCMP2
rw |
TIMxCMP1
rw |
TIMxREP
rw |
TIMxPER
rw |
TIMxCNT
rw |
TIMxDIER
rw |
TIMxICR
rw |
TIMxCR
rw |
Burst DMA Timerx update Register
Offset: 0x6C, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMxFLTR
rw |
TIMxOUTR
rw |
TIMxCHPR
rw |
TIMxRSTR
rw |
TIMxEEFR2
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMxEEFR1
rw |
TIMxRST2R
rw |
TIMxSET2R
rw |
TIMxRST1R
rw |
TIMxSET1R
rw |
TIMx_DTxR
rw |
TIMxCMP4
rw |
TIMxCMP3
rw |
TIMxCMP2
rw |
TIMxCMP1
rw |
TIMxREP
rw |
TIMxPER
rw |
TIMxCNT
rw |
TIMxDIER
rw |
TIMxICR
rw |
TIMxCR
rw |
Burst DMA Data Register
Offset: 0x70, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BDMADR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BDMADR
rw |
|||||||||||||||
0x40017400: High Resolution Timer: Master Timers
54/54 fields covered. Toggle Registers.
Master Timer Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCNT
rw |
|||||||||||||||
Master Timer Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MPER
rw |
|||||||||||||||
Master Timer Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MREP
rw |
|||||||||||||||
Master Timer Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCMP1
rw |
|||||||||||||||
Master Timer Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCMP2
rw |
|||||||||||||||
Master Timer Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCMP3
rw |
|||||||||||||||
Master Timer Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCMP4
rw |
|||||||||||||||
0x40017480: High Resolution Timer: TIMA
359/359 fields covered. Toggle Registers.
Timerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
19/19 fields covered.
Bits 12-13: Delayed CMP2 mode.
Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
Bits 14-15: Delayed CMP4 mode.
Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match
Bits 28-31: Update Gating.
Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3
TIMxDIER5
Offset: 0xC, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DLYPRTDE
rw |
RSTDE
rw |
RSTx2DE
rw |
SETx2DE
rw |
RSTx1DE
rw |
SETx1DE
rw |
CPT2DE
rw |
CPT1DE
rw |
UPDDE
rw |
REPDE
rw |
CMP4DE
rw |
CMP3DE
rw |
CMP2DE
rw |
CMP1DE
rw |
||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DLYPRTIE
rw |
RSTIE
rw |
RSTx2IE
rw |
SETx2IE
rw |
RSTx1IE
rw |
SETx1IE
rw |
CPT2IE
rw |
CPT1IE
rw |
UPDIE
rw |
REPIE
rw |
CMP4IE
rw |
CMP3IE
rw |
CMP2IE
rw |
CMP1IE
rw |
Timerx Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTx
rw |
|||||||||||||||
Timerx Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PERx
rw |
|||||||||||||||
Timerx Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REPx
rw |
|||||||||||||||
Timerx Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 1 Compound Register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REPx
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP2x
rw |
|||||||||||||||
Timerx Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP3x
rw |
|||||||||||||||
Timerx Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP4x
rw |
|||||||||||||||
Timerx Capture 1 Register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT1x
r |
|||||||||||||||
Timerx Capture 2 Register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT2x
r |
|||||||||||||||
Timerx Output1 Set Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output1 Reset Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx Output2 Set Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output2 Reset Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx External Event Filtering Register 1
Offset: 0x4C, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 1 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 2 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 3 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 4 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 5 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Timerx External Event Filtering Register 2
Offset: 0x50, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 6 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 7 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 8 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 9 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 10 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
TimerA Reset Register
Offset: 0x54, reset: 0x00000000, access: read-write
30/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMECMP4
rw |
TIMECMP2
rw |
TIMECMP1
rw |
TIMDCMP4
rw |
TIMDCMP2
rw |
TIMDCMP1
rw |
TIMCCMP4
rw |
TIMCCMP2
rw |
TIMCCMP1
rw |
TIMBCMP4
rw |
TIMBCMP2
rw |
TIMBCMP1
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP2
rw |
UPDT
rw |
Timerx Chopper Register
Offset: 0x58, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STRTPW
rw |
CARDTY
rw |
CARFRQ
rw |
|||||||||||||
Timerx Capture 2 Control Register
Offset: 0x5C, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
||||
CPT2xCR
Offset: 0x60, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
||||
Timerx Output Register
Offset: 0x64, reset: 0x00000000, access: read-write
15/15 fields covered.
Bits 4-5: Output 1 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
Bits 10-12: Delayed Protection.
Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7
Bits 20-21: Output 2 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
0x40017500: High Resolution Timer: TIMB
359/359 fields covered. Toggle Registers.
Timerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
19/19 fields covered.
Bits 12-13: Delayed CMP2 mode.
Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
Bits 14-15: Delayed CMP4 mode.
Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match
Bits 28-31: Update Gating.
Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3
TIMxDIER5
Offset: 0xC, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DLYPRTDE
rw |
RSTDE
rw |
RSTx2DE
rw |
SETx2DE
rw |
RSTx1DE
rw |
SETx1DE
rw |
CPT2DE
rw |
CPT1DE
rw |
UPDDE
rw |
REPDE
rw |
CMP4DE
rw |
CMP3DE
rw |
CMP2DE
rw |
CMP1DE
rw |
||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DLYPRTIE
rw |
RSTIE
rw |
RSTx2IE
rw |
SETx2IE
rw |
RSTx1IE
rw |
SETx1IE
rw |
CPT2IE
rw |
CPT1IE
rw |
UPDIE
rw |
REPIE
rw |
CMP4IE
rw |
CMP3IE
rw |
CMP2IE
rw |
CMP1IE
rw |
Timerx Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTx
rw |
|||||||||||||||
Timerx Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PERx
rw |
|||||||||||||||
Timerx Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REPx
rw |
|||||||||||||||
Timerx Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 1 Compound Register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REPx
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP2x
rw |
|||||||||||||||
Timerx Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP3x
rw |
|||||||||||||||
Timerx Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP4x
rw |
|||||||||||||||
Timerx Capture 1 Register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT1x
r |
|||||||||||||||
Timerx Capture 2 Register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT2x
r |
|||||||||||||||
Timerx Output1 Set Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output1 Reset Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx Output2 Set Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output2 Reset Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx External Event Filtering Register 1
Offset: 0x4C, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 1 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 2 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 3 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 4 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 5 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Timerx External Event Filtering Register 2
Offset: 0x50, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 6 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 7 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 8 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 9 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 10 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
TimerA Reset Register
Offset: 0x54, reset: 0x00000000, access: read-write
30/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMECMP4
rw |
TIMECMP2
rw |
TIMECMP1
rw |
TIMDCMP4
rw |
TIMDCMP2
rw |
TIMDCMP1
rw |
TIMCCMP4
rw |
TIMCCMP2
rw |
TIMCCMP1
rw |
TIMACMP4
rw |
TIMACMP2
rw |
TIMACMP1
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP2
rw |
UPDT
rw |
Timerx Chopper Register
Offset: 0x58, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STRTPW
rw |
CARDTY
rw |
CARFRQ
rw |
|||||||||||||
Timerx Capture 2 Control Register
Offset: 0x5C, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
CPT2xCR
Offset: 0x60, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
Timerx Output Register
Offset: 0x64, reset: 0x00000000, access: read-write
15/15 fields covered.
Bits 4-5: Output 1 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
Bits 10-12: Delayed Protection.
Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7
Bits 20-21: Output 2 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
0x40017580: High Resolution Timer: TIMC
359/359 fields covered. Toggle Registers.
Timerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
19/19 fields covered.
Bits 12-13: Delayed CMP2 mode.
Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
Bits 14-15: Delayed CMP4 mode.
Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match
Bits 28-31: Update Gating.
Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3
TIMxDIER5
Offset: 0xC, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DLYPRTDE
rw |
RSTDE
rw |
RSTx2DE
rw |
SETx2DE
rw |
RSTx1DE
rw |
SETx1DE
rw |
CPT2DE
rw |
CPT1DE
rw |
UPDDE
rw |
REPDE
rw |
CMP4DE
rw |
CMP3DE
rw |
CMP2DE
rw |
CMP1DE
rw |
||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DLYPRTIE
rw |
RSTIE
rw |
RSTx2IE
rw |
SETx2IE
rw |
RSTx1IE
rw |
SETx1IE
rw |
CPT2IE
rw |
CPT1IE
rw |
UPDIE
rw |
REPIE
rw |
CMP4IE
rw |
CMP3IE
rw |
CMP2IE
rw |
CMP1IE
rw |
Timerx Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTx
rw |
|||||||||||||||
Timerx Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PERx
rw |
|||||||||||||||
Timerx Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REPx
rw |
|||||||||||||||
Timerx Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 1 Compound Register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REPx
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP2x
rw |
|||||||||||||||
Timerx Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP3x
rw |
|||||||||||||||
Timerx Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP4x
rw |
|||||||||||||||
Timerx Capture 1 Register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT1x
r |
|||||||||||||||
Timerx Capture 2 Register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT2x
r |
|||||||||||||||
Timerx Output1 Set Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output1 Reset Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx Output2 Set Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output2 Reset Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx External Event Filtering Register 1
Offset: 0x4C, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 1 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 2 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 3 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 4 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 5 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Timerx External Event Filtering Register 2
Offset: 0x50, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 6 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 7 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 8 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 9 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 10 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
TimerA Reset Register
Offset: 0x54, reset: 0x00000000, access: read-write
30/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMECMP4
rw |
TIMECMP2
rw |
TIMECMP1
rw |
TIMDCMP4
rw |
TIMDCMP2
rw |
TIMDCMP1
rw |
TIMBCMP4
rw |
TIMBCMP2
rw |
TIMBCMP1
rw |
TIMACMP4
rw |
TIMACMP2
rw |
TIMACMP1
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP2
rw |
UPDT
rw |
Timerx Chopper Register
Offset: 0x58, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STRTPW
rw |
CARDTY
rw |
CARFRQ
rw |
|||||||||||||
Timerx Capture 2 Control Register
Offset: 0x5C, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
CPT2xCR
Offset: 0x60, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
Timerx Output Register
Offset: 0x64, reset: 0x00000000, access: read-write
15/15 fields covered.
Bits 4-5: Output 1 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
Bits 10-12: Delayed Protection.
Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7
Bits 20-21: Output 2 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
0x40017600: High Resolution Timer: TIMD
359/359 fields covered. Toggle Registers.
Timerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
19/19 fields covered.
Bits 12-13: Delayed CMP2 mode.
Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
Bits 14-15: Delayed CMP4 mode.
Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match
Bits 28-31: Update Gating.
Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3
TIMxDIER5
Offset: 0xC, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DLYPRTDE
rw |
RSTDE
rw |
RSTx2DE
rw |
SETx2DE
rw |
RSTx1DE
rw |
SETx1DE
rw |
CPT2DE
rw |
CPT1DE
rw |
UPDDE
rw |
REPDE
rw |
CMP4DE
rw |
CMP3DE
rw |
CMP2DE
rw |
CMP1DE
rw |
||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DLYPRTIE
rw |
RSTIE
rw |
RSTx2IE
rw |
SETx2IE
rw |
RSTx1IE
rw |
SETx1IE
rw |
CPT2IE
rw |
CPT1IE
rw |
UPDIE
rw |
REPIE
rw |
CMP4IE
rw |
CMP3IE
rw |
CMP2IE
rw |
CMP1IE
rw |
Timerx Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTx
rw |
|||||||||||||||
Timerx Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PERx
rw |
|||||||||||||||
Timerx Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REPx
rw |
|||||||||||||||
Timerx Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 1 Compound Register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REPx
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP2x
rw |
|||||||||||||||
Timerx Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP3x
rw |
|||||||||||||||
Timerx Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP4x
rw |
|||||||||||||||
Timerx Capture 1 Register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT1x
r |
|||||||||||||||
Timerx Capture 2 Register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT2x
r |
|||||||||||||||
Timerx Output1 Set Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output1 Reset Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx Output2 Set Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output2 Reset Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx External Event Filtering Register 1
Offset: 0x4C, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 1 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 2 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 3 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 4 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 5 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Timerx External Event Filtering Register 2
Offset: 0x50, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 6 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 7 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 8 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 9 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 10 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
TimerA Reset Register
Offset: 0x54, reset: 0x00000000, access: read-write
30/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMECMP4
rw |
TIMECMP2
rw |
TIMECMP1
rw |
TIMCCMP4
rw |
TIMCCMP2
rw |
TIMCCMP1
rw |
TIMBCMP4
rw |
TIMBCMP2
rw |
TIMBCMP1
rw |
TIMACMP4
rw |
TIMACMP2
rw |
TIMACMP1
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP2
rw |
UPDT
rw |
Timerx Chopper Register
Offset: 0x58, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STRTPW
rw |
CARDTY
rw |
CARFRQ
rw |
|||||||||||||
Timerx Capture 2 Control Register
Offset: 0x5C, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
CPT2xCR
Offset: 0x60, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TECMP2
rw |
TECMP1
rw |
TE1RST
rw |
TE1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
Timerx Output Register
Offset: 0x64, reset: 0x00000000, access: read-write
15/15 fields covered.
Bits 4-5: Output 1 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
Bits 10-12: Delayed Protection.
Allowed values:
0: Output1_EE8: Output 1 delayed idle on external event 8
1: Output2_EE8: Output 2 delayed idle on external event 8
2: Output1_2_EE8: Output 1 and 2 delayed idle on external event 8
3: Balanced_EE8: Balanced idle on external event 8
4: Output1_EE9: Output 1 delayed idle on external event 9
5: Output2_EE9: Output 2 delayed idle on external event 9
6: Output1_2_EE9: Output 1 and 2 delayed idle on external event 9
7: Balanced_EE9: Balanced idle on external event 9
Bits 20-21: Output 2 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
0x40017680: High Resolution Timer: TIME
359/359 fields covered. Toggle Registers.
Timerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
19/19 fields covered.
Bits 12-13: Delayed CMP2 mode.
Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
Bits 14-15: Delayed CMP4 mode.
Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match
Bits 28-31: Update Gating.
Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3
TIMxDIER5
Offset: 0xC, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DLYPRTDE
rw |
RSTDE
rw |
RSTx2DE
rw |
SETx2DE
rw |
RSTx1DE
rw |
SETx1DE
rw |
CPT2DE
rw |
CPT1DE
rw |
UPDDE
rw |
REPDE
rw |
CMP4DE
rw |
CMP3DE
rw |
CMP2DE
rw |
CMP1DE
rw |
||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DLYPRTIE
rw |
RSTIE
rw |
RSTx2IE
rw |
SETx2IE
rw |
RSTx1IE
rw |
SETx1IE
rw |
CPT2IE
rw |
CPT1IE
rw |
UPDIE
rw |
REPIE
rw |
CMP4IE
rw |
CMP3IE
rw |
CMP2IE
rw |
CMP1IE
rw |
Timerx Counter Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTx
rw |
|||||||||||||||
Timerx Period Register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PERx
rw |
|||||||||||||||
Timerx Repetition Register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REPx
rw |
|||||||||||||||
Timerx Compare 1 Register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 1 Compound Register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REPx
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP1x
rw |
|||||||||||||||
Timerx Compare 2 Register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP2x
rw |
|||||||||||||||
Timerx Compare 3 Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP3x
rw |
|||||||||||||||
Timerx Compare 4 Register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP4x
rw |
|||||||||||||||
Timerx Capture 1 Register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT1x
r |
|||||||||||||||
Timerx Capture 2 Register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CPT2x
r |
|||||||||||||||
Timerx Output1 Set Register
Offset: 0x3C, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output1 Reset Register
Offset: 0x40, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx Output2 Set Register
Offset: 0x44, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SST
rw |
Timerx Output2 Reset Register
Offset: 0x48, reset: 0x00000000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UPDATE
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
TIMEVNT9
rw |
TIMEVNT8
rw |
TIMEVNT7
rw |
TIMEVNT6
rw |
TIMEVNT5
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMEVNT4
rw |
TIMEVNT3
rw |
TIMEVNT2
rw |
TIMEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP3
rw |
CMP2
rw |
CMP1
rw |
PER
rw |
RESYNC
rw |
SRT
rw |
Timerx External Event Filtering Register 1
Offset: 0x4C, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 1 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 2 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 3 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 4 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 5 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Timerx External Event Filtering Register 2
Offset: 0x50, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 1-4: External Event 6 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 7-10: External Event 7 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 13-16: External Event 8 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 19-22: External Event 9 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
Bits 25-28: External Event 10 filter.
Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source
TimerA Reset Register
Offset: 0x54, reset: 0x00000000, access: read-write
30/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIMDCMP4
rw |
TIMDCMP2
rw |
TIMDCMP1
rw |
TIMCCMP4
rw |
TIMCCMP2
rw |
TIMCCMP1
rw |
TIMBCMP4
rw |
TIMBCMP2
rw |
TIMBCMP1
rw |
TIMACMP4
rw |
TIMACMP2
rw |
TIMACMP1
rw |
EXTEVNT10
rw |
EXTEVNT9
rw |
EXTEVNT8
rw |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTEVNT7
rw |
EXTEVNT6
rw |
EXTEVNT5
rw |
EXTEVNT4
rw |
EXTEVNT3
rw |
EXTEVNT2
rw |
EXTEVNT1
rw |
MSTCMP4
rw |
MSTCMP3
rw |
MSTCMP2
rw |
MSTCMP1
rw |
MSTPER
rw |
CMP4
rw |
CMP2
rw |
UPDT
rw |
Timerx Chopper Register
Offset: 0x58, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STRTPW
rw |
CARDTY
rw |
CARFRQ
rw |
|||||||||||||
Timerx Capture 2 Control Register
Offset: 0x5C, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
CPT2xCR
Offset: 0x60, reset: 0x00000000, access: read-write
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDCMP2
rw |
TDCMP1
rw |
TD1RST
rw |
TD1SET
rw |
TCCMP2
rw |
TCCMP1
rw |
TC1RST
rw |
TC1SET
rw |
TBCMP2
rw |
TBCMP1
rw |
TB1RST
rw |
TB1SET
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TACMP2
rw |
TACMP1
rw |
TA1RST
rw |
TA1SET
rw |
EXEV10CPT
rw |
EXEV9CPT
rw |
EXEV8CPT
rw |
EXEV7CPT
rw |
EXEV6CPT
rw |
EXEV5CPT
rw |
EXEV4CPT
rw |
EXEV3CPT
rw |
EXEV2CPT
rw |
EXEV1CPT
rw |
UPDCPT
rw |
SWCPT
rw |
Timerx Output Register
Offset: 0x64, reset: 0x00000000, access: read-write
15/15 fields covered.
Bits 4-5: Output 1 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
Bits 10-12: Delayed Protection.
Allowed values:
0: Output1_EE8: Output 1 delayed idle on external event 8
1: Output2_EE8: Output 2 delayed idle on external event 8
2: Output1_2_EE8: Output 1 and 2 delayed idle on external event 8
3: Balanced_EE8: Balanced idle on external event 8
4: Output1_EE9: Output 1 delayed idle on external event 9
5: Output2_EE9: Output 2 delayed idle on external event 9
6: Output1_2_EE9: Output 1 and 2 delayed idle on external event 9
7: Balanced_EE9: Balanced idle on external event 9
Bits 20-21: Output 2 Fault state.
Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event
0x40005400: Inter-integrated circuit
76/77 fields covered. Toggle Registers.
Control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
20/21 fields covered.
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xC, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40005800: Inter-integrated circuit
76/77 fields covered. Toggle Registers.
Control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
20/21 fields covered.
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xC, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40007800: Inter-integrated circuit
76/77 fields covered. Toggle Registers.
Control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
20/21 fields covered.
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xC, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40003400: Serial peripheral interface/Inter-IC2
52/52 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 0x00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40004000: Serial peripheral interface/Inter-IC2
52/52 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 0x00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003000: Independent watchdog
7/7 fields covered. Toggle Registers.
Key register
Offset: 0x0, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Prescaler register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR
rw |
|||||||||||||||
Reload register
Offset: 0x8, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RL
rw |
|||||||||||||||
Status register
Offset: 0xC, reset: 0x00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WVU
r |
RVU
r |
PVU
r |
|||||||||||||
Window register
Offset: 0x10, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WIN
rw |
|||||||||||||||
0xE000ED90: Memory protection unit
6/19 fields covered. Toggle Registers.
MPU type register
Offset: 0x0, reset: 0X00000800, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IREGION
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DREGION
r |
SEPARATE
r |
||||||||||||||
MPU control register
Offset: 0x4, reset: 0X00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRIVDEFENA
r |
HFNMIENA
r |
ENABLE
r |
|||||||||||||
MPU region number register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REGION
rw |
|||||||||||||||
MPU region base address register
Offset: 0xC, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDR
rw |
VALID
rw |
REGION
rw |
|||||||||||||
0xE000E100: Nested Vectored Interrupt Controller
3/99 fields covered. Toggle Registers.
Interrupt Set-Enable Register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x84, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x100, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x104, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x108, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x180, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x184, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x188, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x200, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x204, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x208, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Priority Register
Offset: 0x300, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x304, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x308, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x30C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x310, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x314, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x318, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x31C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x320, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x324, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x328, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x32C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x330, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x334, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x338, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x33C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x340, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x344, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x348, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x34C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x350, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
0xE000EF00: Nested vectored interrupt controller
0/1 fields covered. Toggle Registers.
Software trigger interrupt register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INTID
rw |
|||||||||||||||
1073807360: Operational Amplifier
16/16 fields covered. Toggle Registers.
OPAMP2 control register
Offset: 0x60, reset: 0, access: Unspecified
16/16 fields covered.
Bits 14-17: Gain in PGA mode.
Allowed values:
0: Gain2: Gain 2
1: Gain4: Gain 4
2: Gain8: Gain 8
4: Gain16: Gain 16
8: Gain2_VM0: Gain 2, feedback connected to VM0
9: Gain4_VM0: Gain 4, feedback connected to VM0
10: Gain8_VM0: Gain 8, feedback connected to VM0
11: Gain16_VM0: Gain 16, feedback connected to VM0
12: Gain2_VM1: Gain 2, feedback connected to VM1
13: Gain4_VM1: Gain 4, feedback connected to VM1
14: Gain8_VM1: Gain 8, feedback connected to VM1
15: Gain16_VM1: Gain 16, feedback connected to VM1
0x40007000: Power control
4/12 fields covered. Toggle Registers.
0x40021000: Reset and clock control
120/120 fields covered. Toggle Registers.
Clock configuration register (RCC_CFGR)
Offset: 0x4, reset: 0x00000000, access: Unspecified
11/11 fields covered.
Bits 4-7: AHB prescaler.
Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
Bits 18-21: PLL Multiplication Factor.
Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16
Bits 24-26: Microcontroller clock output.
Allowed values:
0: NoMCO: MCO output disabled, no clock on MCO
2: LSI: Internal low speed (LSI) oscillator clock selected
3: LSE: External low speed (LSE) oscillator clock selected
4: SYSCLK: System clock selected
5: HSI: Internal RC 8 MHz (HSI) oscillator clock selected
6: HSE: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
Bits 28-30: Microcontroller Clock Output Prescaler.
Allowed values:
0: Div1: MCO is divided by 1
1: Div2: MCO is divided by 2
2: Div4: MCO is divided by 4
3: Div8: MCO is divided by 8
4: Div16: MCO is divided by 16
5: Div32: MCO is divided by 32
6: Div64: MCO is divided by 64
7: Div128: MCO is divided by 128
Clock configuration register 2
Offset: 0x2C, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADC12PRES
rw |
PREDIV
rw |
||||||||||||||
Bits 0-3: PREDIV division factor.
Allowed values:
0: Div1: PREDIV input clock not divided
1: Div2: PREDIV input clock divided by 2
2: Div3: PREDIV input clock divided by 3
3: Div4: PREDIV input clock divided by 4
4: Div5: PREDIV input clock divided by 5
5: Div6: PREDIV input clock divided by 6
6: Div7: PREDIV input clock divided by 7
7: Div8: PREDIV input clock divided by 8
8: Div9: PREDIV input clock divided by 9
9: Div10: PREDIV input clock divided by 10
10: Div11: PREDIV input clock divided by 11
11: Div12: PREDIV input clock divided by 12
12: Div13: PREDIV input clock divided by 13
13: Div14: PREDIV input clock divided by 14
14: Div15: PREDIV input clock divided by 15
15: Div16: PREDIV input clock divided by 16
Bits 4-8: ADC1 and ADC2 prescaler.
Allowed values:
0: NoClock: No clock
16: Div1: PLL clock not divided
17: Div2: PLL clock divided by 2
18: Div4: PLL clock divided by 4
19: Div6: PLL clock divided by 6
20: Div8: PLL clock divided by 8
21: Div10: PLL clock divided by 10
22: Div12: PLL clock divided by 12
23: Div16: PLL clock divided by 16
24: Div32: PLL clock divided by 32
25: Div64: PLL clock divided by 64
26: Div128: PLL clock divided by 128
27: Div256: PLL clock divided by 256
Clock configuration register 3
Offset: 0x30, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIM1SW
rw |
I2C1SW
rw |
USART1SW
rw |
|||||||||||||
0x40002800: Real-time clock
135/157 fields covered. Toggle Registers.
control register
Offset: 0x8, reset: 0x00000000, access: read-write
20/20 fields covered.
Bits 0-2: Wakeup clock selection.
Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
Bit 5: Bypass the shadow registers.
Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
prescaler register
Offset: 0x10, reset: 0x007F00FF, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PREDIV_A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PREDIV_S
rw |
|||||||||||||||
wakeup timer register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUT
rw |
|||||||||||||||
write protection register
Offset: 0x24, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
sub second register
Offset: 0x28, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
shift control register
Offset: 0x2C, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD1S
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SUBFS
w |
|||||||||||||||
timestamp sub second register
Offset: 0x38, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
calibration register
Offset: 0x3C, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALP
rw |
CALW8
rw |
CALW16
rw |
CALM
rw |
||||||||||||
tamper and alternate function configuration register
Offset: 0x40, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PC15MODE
rw |
PC15VALUE
rw |
PC14MODE
rw |
PC14VALUE
rw |
PC13MODE
rw |
PC13VALUE
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
TAMPTS
rw |
TAMP3TRG
rw |
TAMP3E
rw |
TAMP2TRG
rw |
TAMP2E
rw |
TAMPIE
rw |
TAMP1TRG
rw |
TAMP1E
rw |
||||
Bit 1: Active level for tamper 1.
Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event
Bit 4: Active level for tamper 2.
Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event
Bit 6: Active level for tamper 3.
Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event
Bits 8-10: Tamper sampling frequency.
Allowed values:
0: Div32768: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
1: Div16384: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
2: Div8192: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
3: Div4096: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
4: Div2048: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
5: Div1024: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
6: Div512: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
7: Div256: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bits 11-12: Tamper filter count.
Allowed values:
0: Immediate: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)
1: Samples2: Tamper event is activated after 2 consecutive samples at the active level
2: Samples4: Tamper event is activated after 4 consecutive samples at the active level
3: Samples8: Tamper event is activated after 8 consecutive samples at the active level
alarm A sub second register
Offset: 0x44, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
alarm B sub second register
Offset: 0x48, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
backup register
Offset: 0x50, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x54, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x58, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x5C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x60, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x64, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x68, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x6C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x70, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x74, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x78, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x7C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x84, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x8C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x90, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x94, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x98, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x9C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xA0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xA4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xA8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xAC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xB0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xB4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xB8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xBC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xC0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xC4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xC8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0xCC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
0xE000ED00: System control block
5/74 fields covered. Toggle Registers.
CPUID base register
Offset: 0x0, reset: 0x410FC241, access: read-only
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Implementer
r |
Variant
r |
Constant
r |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PartNo
r |
Revision
r |
||||||||||||||
Interrupt control and state register
Offset: 0x4, reset: 0x00000000, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
rw |
PENDSTSET
rw |
PENDSTCLR
rw |
ISRPENDING
rw |
VECTPENDING
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTPENDING
rw |
RETTOBASE
rw |
VECTACTIVE
rw |
|||||||||||||
Vector table offset register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TBLOFF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TBLOFF
rw |
|||||||||||||||
Application interrupt and reset control register
Offset: 0xC, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VECTKEYSTAT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ENDIANESS
rw |
PRIGROUP
rw |
SYSRESETREQ
rw |
VECTCLRACTIVE
rw |
VECTRESET
rw |
|||||||||||
System control register
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SEVEONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
|||||||||||||
Configuration and control register
Offset: 0x14, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN__TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
||||||||||
System handler priority registers
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_6
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRI_5
rw |
PRI_4
rw |
||||||||||||||
System handler priority registers
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_11
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler priority registers
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_15
rw |
PRI_14
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler control and state register
Offset: 0x24, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
|||||
Configurable fault status register
Offset: 0x28, reset: 0x00000000, access: read-write
0/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
IACCVIOL
rw |
||||
Hard fault status register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DEBUG_VT
rw |
FORCED
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTTBL
rw |
|||||||||||||||
Memory management fault address register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMFAR
rw |
|||||||||||||||
Bus fault address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFAR
rw |
|||||||||||||||
Auxiliary fault status register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IMPDEF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IMPDEF
rw |
|||||||||||||||
0xE000E008: System control block ACTLR
0/5 fields covered. Toggle Registers.
Auxiliary control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DISOOFP
rw |
DISFPCA
rw |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
|||||||||||
0x40013000: Serial peripheral interface/Inter-IC2
52/52 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 0x00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003800: Serial peripheral interface/Inter-IC2
52/52 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 0x00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003C00: Serial peripheral interface/Inter-IC2
52/52 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 0x00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0xE000E010: SysTick timer
0/9 fields covered. Toggle Registers.
SysTick control and status register
Offset: 0x0, reset: 0X00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COUNTFLAG
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLKSOURCE
rw |
TICKINT
rw |
ENABLE
rw |
|||||||||||||
SysTick reload value register
Offset: 0x4, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RELOAD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RELOAD
rw |
|||||||||||||||
SysTick current value register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CURRENT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CURRENT
rw |
|||||||||||||||
SysTick calibration value register
Offset: 0xC, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NOREF
rw |
SKEW
rw |
TENMS
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TENMS
rw |
|||||||||||||||
0x40010000: System configuration controller
53/53 fields covered. Toggle Registers.
configuration register 1
Offset: 0x0, reset: 0x00000000, access: read-write
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FPU_IE5
rw |
FPU_IE4
rw |
FPU_IE3
rw |
FPU_IE2
rw |
FPU_IE1
rw |
FPU_IE0
rw |
ENCODER_MODE
rw |
I2C2_FMP
rw |
I2C1_FMP
rw |
I2C_PB9_FMP
rw |
I2C_PB8_FMP
rw |
I2C_PB7_FMP
rw |
I2C_PB6_FMP
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DAC2_CH1_DMA_RMP
rw |
TIM7_DAC1_CH2_DMA_RMP
rw |
TIM6_DAC1_CH1_DMA_RMP
rw |
TIM17_DMA_RMP
rw |
TIM16_DMA_RMP
rw |
DAC_TRIG_RMP
rw |
TIM1_ITR3_RMP
rw |
MEM_MODE
rw |
||||||||
CCM SRAM protection register
Offset: 0x4, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PAGE3_WP
rw |
PAGE2_WP
rw |
PAGE1_WP
rw |
PAGE0_WP
rw |
||||||||||||
external interrupt configuration register 1
Offset: 0x8, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI3
rw |
EXTI2
rw |
EXTI1
rw |
EXTI0
rw |
||||||||||||
Bits 0-3: EXTI 0 configuration bits.
Allowed values:
0: PA0: Select PA0 as the source input for the EXTI0 external interrupt
1: PB0: Select PB0 as the source input for the EXTI0 external interrupt
2: PC0: Select PC0 as the source input for the EXTI0 external interrupt
3: PD0: Select PD0 as the source input for the EXTI0 external interrupt
4: PE0: Select PE0 as the source input for the EXTI0 external interrupt
5: PF0: Select PF0 as the source input for the EXTI0 external interrupt
Bits 4-7: EXTI 1 configuration bits.
Allowed values:
0: PA1: Select PA1 as the source input for the EXTI1 external interrupt
1: PB1: Select PB1 as the source input for the EXTI1 external interrupt
2: PC1: Select PC1 as the source input for the EXTI1 external interrupt
3: PD1: Select PD1 as the source input for the EXTI1 external interrupt
4: PE1: Select PE1 as the source input for the EXTI1 external interrupt
5: PF1: Select PF1 as the source input for the EXTI1 external interrupt
Bits 8-11: EXTI 2 configuration bits.
Allowed values:
0: PA2: Select PA2 as the source input for the EXTI2 external interrupt
1: PB2: Select PB2 as the source input for the EXTI2 external interrupt
2: PC2: Select PC2 as the source input for the EXTI2 external interrupt
3: PD2: Select PD2 as the source input for the EXTI2 external interrupt
4: PE2: Select PE2 as the source input for the EXTI2 external interrupt
5: PF2: Select PF2 as the source input for the EXTI2 external interrupt
Bits 12-15: EXTI 3 configuration bits.
Allowed values:
0: PA3: Select PA3 as the source input for the EXTI3 external interrupt
1: PB3: Select PB3 as the source input for the EXTI3 external interrupt
2: PC3: Select PC3 as the source input for the EXTI3 external interrupt
3: PD3: Select PD3 as the source input for the EXTI3 external interrupt
4: PE3: Select PE3 as the source input for the EXTI3 external interrupt
external interrupt configuration register 2
Offset: 0xC, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI7
rw |
EXTI6
rw |
EXTI5
rw |
EXTI4
rw |
||||||||||||
Bits 0-3: EXTI 4 configuration bits.
Allowed values:
0: PA4: Select PA4 as the source input for the EXTI4 external interrupt
1: PB4: Select PB4 as the source input for the EXTI4 external interrupt
2: PC4: Select PC4 as the source input for the EXTI4 external interrupt
3: PD4: Select PD4 as the source input for the EXTI4 external interrupt
4: PE4: Select PE4 as the source input for the EXTI4 external interrupt
5: PF4: Select PF4 as the source input for the EXTI4 external interrupt
Bits 4-7: EXTI 5 configuration bits.
Allowed values:
0: PA5: Select PA5 as the source input for the EXTI5 external interrupt
1: PB5: Select PB5 as the source input for the EXTI5 external interrupt
2: PC5: Select PC5 as the source input for the EXTI5 external interrupt
3: PD5: Select PD5 as the source input for the EXTI5 external interrupt
4: PE5: Select PE5 as the source input for the EXTI5 external interrupt
5: PF5: Select PF5 as the source input for the EXTI5 external interrupt
Bits 8-11: EXTI 6 configuration bits.
Allowed values:
0: PA6: Select PA6 as the source input for the EXTI6 external interrupt
1: PB6: Select PB6 as the source input for the EXTI6 external interrupt
2: PC6: Select PC6 as the source input for the EXTI6 external interrupt
3: PD6: Select PD6 as the source input for the EXTI6 external interrupt
4: PE6: Select PE6 as the source input for the EXTI6 external interrupt
5: PF6: Select PF6 as the source input for the EXTI6 external interrupt
Bits 12-15: EXTI 7 configuration bits.
Allowed values:
0: PA7: Select PA7 as the source input for the EXTI7 external interrupt
1: PB7: Select PB7 as the source input for the EXTI7 external interrupt
2: PC7: Select PC7 as the source input for the EXTI7 external interrupt
3: PD7: Select PD7 as the source input for the EXTI7 external interrupt
4: PE7: Select PE7 as the source input for the EXTI7 external interrupt
external interrupt configuration register 3
Offset: 0x10, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI11
rw |
EXTI10
rw |
EXTI9
rw |
EXTI8
rw |
||||||||||||
Bits 0-3: EXTI 8 configuration bits.
Allowed values:
0: PA8: Select PA8 as the source input for the EXTI8 external interrupt
1: PB8: Select PB8 as the source input for the EXTI8 external interrupt
2: PC8: Select PC8 as the source input for the EXTI8 external interrupt
3: PD8: Select PD8 as the source input for the EXTI8 external interrupt
4: PE8: Select PE8 as the source input for the EXTI8 external interrupt
Bits 4-7: EXTI 9 configuration bits.
Allowed values:
0: PA9: Select PA9 as the source input for the EXTI9 external interrupt
1: PB9: Select PB9 as the source input for the EXTI9 external interrupt
2: PC9: Select PC9 as the source input for the EXTI9 external interrupt
3: PD9: Select PD9 as the source input for the EXTI9 external interrupt
4: PE9: Select PE9 as the source input for the EXTI9 external interrupt
5: PF9: Select PF9 as the source input for the EXTI9 external interrupt
Bits 8-11: EXTI 10 configuration bits.
Allowed values:
0: PA10: Select PA10 as the source input for the EXTI10 external interrupt
1: PB10: Select PB10 as the source input for the EXTI10 external interrupt
2: PC10: Select PC10 as the source input for the EXTI10 external interrupt
3: PD10: Select PD10 as the source input for the EXTI10 external interrupt
4: PE10: Select PE10 as the source input for the EXTI10 external interrupt
5: PF10: Select PF10 as the source input for the EXTI10 external interrupt
Bits 12-15: EXTI 11 configuration bits.
Allowed values:
0: PA11: Select PA11 as the source input for the EXTI11 external interrupt
1: PB11: Select PB11 as the source input for the EXTI11 external interrupt
2: PC11: Select PC11 as the source input for the EXTI11 external interrupt
3: PD11: Select PD11 as the source input for the EXTI11 external interrupt
4: PE11: Select PE11 as the source input for the EXTI11 external interrupt
external interrupt configuration register 4
Offset: 0x14, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI15
rw |
EXTI14
rw |
EXTI13
rw |
EXTI12
rw |
||||||||||||
Bits 0-3: EXTI 12 configuration bits.
Allowed values:
0: PA12: Select PA12 as the source input for the EXTI12 external interrupt
1: PB12: Select PB12 as the source input for the EXTI12 external interrupt
2: PC12: Select PC12 as the source input for the EXTI12 external interrupt
3: PD12: Select PD12 as the source input for the EXTI12 external interrupt
4: PE12: Select PE12 as the source input for the EXTI12 external interrupt
Bits 4-7: EXTI 13 configuration bits.
Allowed values:
0: PA13: Select PA13 as the source input for the EXTI13 external interrupt
1: PB13: Select PB13 as the source input for the EXTI13 external interrupt
2: PC13: Select PC13 as the source input for the EXTI13 external interrupt
3: PD13: Select PD13 as the source input for the EXTI13 external interrupt
4: PE13: Select PE13 as the source input for the EXTI13 external interrupt
Bits 8-11: EXTI 14 configuration bits.
Allowed values:
0: PA14: Select PA14 as the source input for the EXTI14 external interrupt
1: PB14: Select PB14 as the source input for the EXTI14 external interrupt
2: PC14: Select PC14 as the source input for the EXTI14 external interrupt
3: PD14: Select PD14 as the source input for the EXTI14 external interrupt
4: PE14: Select PE14 as the source input for the EXTI14 external interrupt
Bits 12-15: EXTI 15 configuration bits.
Allowed values:
0: PA15: Select PA15 as the source input for the EXTI15 external interrupt
1: PB15: Select PB15 as the source input for the EXTI15 external interrupt
2: PC15: Select PC15 as the source input for the EXTI15 external interrupt
3: PD15: Select PD15 as the source input for the EXTI15 external interrupt
4: PE15: Select PE15 as the source input for the EXTI15 external interrupt
configuration register 2
Offset: 0x18, reset: 0x0000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SRAM_PEF
rw |
BYP_ADDR_PAR
rw |
PVD_LOCK
rw |
SRAM_PARITY_LOCK
rw |
LOCKUP_LOCK
rw |
|||||||||||
Bit 4: Bypass address bit 29 in parity calculation.
Allowed values:
0: NoBypass: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated
1: Bypass: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated
configuration register 3
Offset: 0x50, reset: 0x0000, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DAC1_TRIG5_RMP
rw |
DAC1_TRIG3_RMP
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADC2_DMA_RMP
rw |
I2C1_TX_DMA_RMP
rw |
I2C1_RX_DMA_RMP
rw |
SPI1_TX_DMA_RMP
rw |
SPI1_RX_DMA_RMP
rw |
|||||||||||
0x40012C00: Advanced timer
78/165 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/9 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/15 fields covered.
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/9 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
capture/compare register 5
Offset: 0x58, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
GC5C3
rw |
GC5C2
rw |
GC5C1
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register 6
Offset: 0x5C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
option registers
Offset: 0x60, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIM1_ETR_ADC4_RMP
rw |
TIM1_ETR_ADC1_RMP
rw |
||||||||||||||
0x40014000: General purpose timers
10/86 fields covered. Toggle Registers.
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SMS_3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSM
rw |
TS
rw |
SMS
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40014400: General-purpose-timers
20/63 fields covered. Toggle Registers.
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1NE
rw |
CC1P
rw |
CC1E
rw |
||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
option register
Offset: 0x50, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x40014800: General purpose timer
10/62 fields covered. Toggle Registers.
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1NE
rw |
CC1P
rw |
CC1E
rw |
||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40000000: General purpose timer
74/104 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/9 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/9 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40000400: General purpose timer
74/97 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40001000: Basic timers
14/15 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40001400: Basic timers
14/15 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40024000: Touch sensing controller
7/163 fields covered. Toggle Registers.
interrupt enable register
Offset: 0x4, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCEIE
rw |
EOAIE
rw |
||||||||||||||
interrupt clear register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCEIC
rw |
EOAIC
rw |
||||||||||||||
interrupt status register
Offset: 0xC, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCEF
rw |
EOAF
rw |
||||||||||||||
I/O hysteresis control register
Offset: 0x10, reset: 0xFFFFFFFF, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
I/O analog switch control register
Offset: 0x18, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
I/O sampling control register
Offset: 0x20, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
I/O channel control register
Offset: 0x28, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
I/O group x counter register
Offset: 0x34, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
r |
|||||||||||||||
0x40013800: Universal synchronous asynchronous receiver-transmitter
103/103 fields covered. Toggle Registers.
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
19/19 fields covered.
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Baud rate register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
0x40004400: Universal synchronous asynchronous receiver-transmitter
103/103 fields covered. Toggle Registers.
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
19/19 fields covered.
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Baud rate register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
0x40004800: Universal synchronous asynchronous receiver-transmitter
103/103 fields covered. Toggle Registers.
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
19/19 fields covered.
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Baud rate register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
0x40002C00: Window watchdog
6/6 fields covered. Toggle Registers.
Control register
Offset: 0x0, reset: 0x0000007F, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDGA
rw |
T
rw |
||||||||||||||
Configuration register
Offset: 0x4, reset: 0x0000007F, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWI
rw |
WDGTB
rw |
W
rw |
|||||||||||||
Status register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWIF
rw |
|||||||||||||||